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0.4 amp output current igbt gate drive optocoupler technical data HCPL-J314 features 0.4 a minimum peak output current high speed response: 0.7 m s max. propagation delay over temp. range ultra high cmr: min. 10 kv/ m s at v cm = 1.5 kv bootstrappable supply current: max. 3 ma wide operating temp. range: -40 c to 100 c wide v cc operating range: 10 v to 30 v over temp. range available in dip8 (single) and so16 (dual) package safety approvals: ul recognized, 3750 v rms for 1 minute. csa approval pending. vde approval pending viorm=891 v peak applications isolated igbt/power mosfet gate drive ac and brushless dc motor drives inverters for appliances industrial inverters switch mode power supplies (smps) uninterruptable power supplies (ups) description the HCPL-J314 family of devices consists of an algaas led optically coupled to an integrated circuit with a power output stage. these optocouplers are ideally suited for driving power igbts and mosfets used in motor control inverter applications. the high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. the voltage and current supplied by this optocoupler makes it ideally suited for directly driving small or medium power igbts. for igbts with higher ratings the hcpl-3150(0.5a) or hcpl-3120 (2.0a) optocouplers can be used. functional diagram truth table led v o off low on high HCPL-J314 a 0.1 m f bypass capacitor must be connected between pins v cc and v ee . caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. 1 3 shield 2 4 8 6 7 5 n/c cathode anode n/c v cc v o v o v ee
2 ordering information specify part number followed by option number (if desired). example : HCPL-J314#xxx no option = standard dip package, 50 per tube. 300 = gull wing surface mount option, 50 per tube. 500 = tape and reel packaging option. hcpl-314j#yyy no option = so16 package. 500 = tape and reel packaging option. selection guide package type part number number of channels 8-pin dip (300 mil) HCPL-J314 1 so16 hcpl-314j 2
3 HCPL-J314 package outline drawings 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. HCPL-J314 yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. 0.20 (0.008) 0.33 (0.013) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) 0.635 ?0.25 (0.025 ?0.010) 12?nom. 0.20 (0.008) 0.33 (0.013) 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.960 (0.390) 4.826 (0.190) typ. 0.381 (0.015) 0.635 (0.025) pad location (for reference only) 1.080 ?0.320 (0.043 ?0.013) 4.19 (0.165) max. 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). tolerances (unless otherwise specified): xx.xx = 0.01 xx.xxx = 0.005 HCPL-J314 yyww lead coplanarity maximum: 0.102 (0.004) standard dip package gull wing surface mount option 300
4 solder reflow temperature profile 240 d t = 115?, 0.3?/sec 0 d t = 100?, 1.5?/sec d t = 145?, 1?/sec time ?minutes temperature ?? 220 200 180 160 140 120 100 80 60 40 20 0 260 123 456789101112 (note: use of non-chlorine activated fluxes is recommended.) regulatory information the HCPL-J314 are pending approval by the following organizations: vde approval under vde 0884/06.92 with v iorm = 891 v peak expected prior to product release. ul approval under ul 1577, component recognition program up to v iso = 3750 v rms expected prior to product release. file e55361. csa approved under csa component acceptance notice #5, file ca 88324 expected prior to product release. vde 0884 insulation characteristics description symbol characteristic unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i - iv for rated mains voltage 300 v rms i - iii for rated mains voltage 600 v rms i-ii climatic classification 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b* v iorm x 1.875=v pr , 100% production test with v pr 1670 v peak t m =1 sec, partial discharge < 5 pc input to output test voltage, method a* v iorm x 1.5=v pr , type and sample test, t m =60 sec, v pr 1336 v peak partial discharge < 5 pc highest allowable overvoltage v iotm 6000 v peak (transient overvoltage t ini = 10 sec) safety-limiting values - maximum values allowed in the event of a failure. case temperature t s 175 c input current** i s,input 400 ma output power** p s, output 1200 mw insulation resistance at t s , v io = 500 v r s >10 9 w * refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section, (vde 0884) for a detailed description of method a and method b partial discharge test profiles. ** refer to the following figure for dependence of p s and i s on ambient temperature.
5 output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 200 600 400 25 800 50 75 100 200 150 175 p s (mw) 125 100 300 500 700 i s (ma) insulation and safety related specifications parameter symbol HCPL-J314 units conditions minimum external air gap l(101) 7.4 mm measured from input terminals (clearance) to output terminals, shortest distance through air. minimum external tracking l(102) 8.0 mm measured from input terminals (creepage) to output terminals, shortest distance path along body. minimum internal plastic gap 0.5 mm through insulation distance (internal clearance) conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance cti >175 v din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 100 c average input current i f(avg) 25 ma 1 peak transient input current (<1 m s pulse i f(tran) 1.0 a width, 300pps) reverse input voltage v r 3v high peak output current i oh(peak) 0.6 a 2 low peak output current i ol(peak) 0.6 a 2 supply voltage v cc -v ee -0.5 35 v output voltage v o(peak) -0.5 v cc v output power dissipation p o 260 mw 3 input power dissipation p i 105 mw 4 lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see package outline drawings section
6 electrical specifications (dc) over recommended operating conditions unless otherwise specified. test parameter symbol min. typ. max. units conditions fig. note high level output current i oh 0.2 a vo = v cc - 4 2 5 0.4 0.5 vo = v cc -10 3 2 low level output current i ol 0.2 0.4 a vo = v ee +2.5 5 5 0.4 0.5 vo = v ee +10 6 2 high level output voltage v oh v cc -4 v cc -1.8 v io = -100 ma 1 6,7 low level output voltage v ol 0.4 1 v io = 100 ma 4 high level supply current i cch 0.7 3 ma io = 0 ma 7,8 14 low level supply current i ccl 1.2 3 ma io = 0 ma threshold input current i flh 5 ma io = 0 ma, 9,15 low to high vo>5 v threshold input voltage v fhl 0.8 v high to low input forward voltage v f 1.2 1.5 1.8 v i f = 10 ma 16 temperature coefficient of d v f / d t a -1.2 mv/ c input forward voltage input reverse breakdown bv r 310 vi r = 100 m a voltage input capacitance c in 60 pf f = 1 mhz, v f = 0 v recommended operating conditions parameter symbol min. max. units note power supply v cc -v ee 10 30 v input current (on) i f(on) 812ma input voltage (off) v f(off) - 3.0 0.8 v operating temperature t a - 40 100 c
7 switching specifications (ac) over recommended operating conditions unless otherwise specified. test parameter symbol min. typ. max. units conditions fig. note propagation delay time to t plh 0.1 0.2 0.7 m s rg = 47 w , 10,11, 14 high output level cg = 3 nf, 12,13, propagation delay time to t phl 0.1 0.3 0.7 m s f = 10 khz, 14,17 low output level duty cycle = propagation delay pdd -0.5 0.5 m s 50%, 10 difference between any i f = 8 ma, two parts or channels v cc = 30 v rise time t r 50 ns fall time t f 50 ns output high level common |cm h | 10 30 kv/ m st a = 25 c, 18 11 mode transient immunity v cm = 1.5 kv output low level common |cm l | 10 30 kv/ m s1812 mode transient immunity package characteristics for each channel unless otherwise specified. test parameter symbol min. typ. max. units conditions fig. note input-output momentary v iso 3750 v rms t a =25 c, 8,9 withstand voltage rh<50% for output-output momentary v o-o 1500 v rms 1 min. 15 withstand voltage input-output resistance r i-o 10 12 w v i-o =500 v 9 input-output capacitance c i-o 1.2 pf freq=1 mhz notes: 1. derate linearly above 70 c free air temperature at a rate of 0.3 ma/ c. 2. maximum pulse width = 10 m s, maximum duty cycle = 0.2%. this value is intended to allow for component tolerances for designs with i o peak minimum = 0.4 a. see application section for additional details on limiting i ol peak. 3. derate linearly above 85 c, free air temperature at the rate of 4.0 mw/ c. 4. input power dissipation does not require derating. 5. maximum pulse width = 50 m s, maximum duty cycle = 0.5%. 6. in this test, v oh is measured with a dc load current. when driving capacitive load v oh will approach v cc as i oh approaches zero amps. 7. maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. in accordance with ul 1577, each HCPL-J314 optocoupler is proof tested by applying an insulation test voltage 3 5000 v rms for 1 second (leakage detection current limit i i-o 5 m a). this test is performed before 100% production test for partial discharge (method b) shown in the vde 0884 insulation characteristics table, if applicable. 9. device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. pdd is the difference between t phl and t plh between any two parts or channels under the same test conditions. 11. common mode transient immunity in the high state is the maximum tolerable |dvcm/dt| of the common mode pulse v cm to assure that the output will remain in the high state (i.e. vo > 6.0 v). 12. common mode transient immunity in a low state is the maximum tolerable |dv cm /dt| of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e. vo < 1.0 v). 13. this load condition approximates the gate load of a 1200 v/25 a igbt. 14. for each channel. the power supply current increases when operating frequency and qg of the driven igbt increases. 15. device considered a two terminal device: channel one output side pins shorted together, and channel two output side pins shorted together.
8 figure 1. v oh vs. temperature. figure 2. i oh vs. temperature. figure 3. v oh vs. i oh . figure 4. v ol vs. temperature. figure 5. i ol vs. temperature. figure 6. v ol vs. i ol . figure 7. i cc vs. temperature. figure 8. i cc vs. v cc . figure 9. i flh vs. temperature. (v oh -v cc ) ?high output voltage drop ?v -50 -2.5 t a ?temperature ?? 125 -25 0 0 25 75 100 50 -2.0 -1.5 -1.0 -0.5 i oh ?output high current ?a -50 0.30 t a ?temperature ?? 125 -25 0.40 0 25 75 100 50 0.32 0.34 0.36 0.38 0 -6 i oh ?output high current ?a 0.6 0 0.2 0.4 -5 -4 -3 -1 (v oh -v cc ) ?output high voltage drop ?v -2 v oh v ol ?output low voltage ?v -50 0.39 t a ?temperature ?? 125 -25 0.44 0 25 75 100 50 0.40 0.41 0.42 0.43 i ol ?output low current ?a -50 0.440 t a ?temperature ?? 125 -25 0.470 0 25 75 100 50 0.450 0.455 0.460 0.465 0.445 i cc ?supply current ?ma -50 0 t a ?temperature ?? 125 -25 1.4 0 25 75 100 50 0.4 0.6 0.8 1.2 0.2 1.0 i cc l i cc h i cc ?supply current ?ma 10 0 v cc ?supply voltage ?v 30 15 1.2 20 25 0.4 0.8 0.2 0.6 1.0 i cc l i cc h i flh ?low to high current threshold ?ma -50 1.5 t a ?temperature ?? 125 -25 3.5 0 25 75 100 50 2.0 2.5 3.0 v ol ?output low voltage ?v 0 0 i ol ?output low current ?ma 700 100 25 400 500 5 20 200 300 600 15 10
9 figure 10. propagation delay vs. v cc . figure 11. propagation delay vs. i f . figure 12. propagation delay vs. temperature. figure 13. propagation delay vs. rg. figure 14. propagation delay vs. cg. figure 15. transfer characteristics. figure 16. input current vs. forward voltage. t p ?propagation delay ?ns 6 0 i f ?forward led current ?ma 18 400 915 12 100 200 300 -50 0 t a ?temperature ?? 125 -25 500 0 25 75 100 50 100 200 300 400 t p ?propagation delay ?ns t plh t phl t p ?propagation delay ?ns 0 200 rg ?series load resistance ? w 200 400 50 150 100 250 300 350 t plh t phl v o ?output voltage ?v 0 -5 i f ?forward led current ?ma 6 25 15 1 35 234 5 5 0 10 20 30 i f ?forward current ?ma 1.2 0 v f ?forward voltage ?v 1.8 25 1.4 1.6 5 10 15 20 t p ?propagation delay ?ns 0 0 cg ?load capacitance ?nf 100 400 20 80 60 100 200 300 t plh t phl 40 t p ?propagation delay ?ns 10 0 v cc ?supply voltage ?v 30 400 15 25 20 100 200 300 t plh t phl
10 figure 17. propagation delay test circuit and waveforms. figure 18. cmr test circuit and waveforms. 0.1 ? v cc = 15 to 30 v 47 w 1 3 i f = 7 to 16 ma v o + + 2 4 8 6 7 5 10 khz 50% duty cycle 500 w 3 nf i f v out t phl t plh t f t r 10% 50% 90% 0.1 ? v cc = 30 v 1 3 i f v o + + 2 4 8 6 7 5 a + b v cm = 1500 v 5 v v cm d t 0 v v o switch at b: i f = 0 ma v o switch at a: i f = 10 ma v ol v oh d t v cm d v d t =
11 applications information eliminating negative igbt gate drive to keep the igbt firmly off, the HCPL-J314 has a very low maximum v ol specification of 1.0 v. minimizing rg and the lead inductance from the HCPL-J314 to the igbt gate and emitter (possibly by mounting the HCPL-J314 on a small pc board directly above the igbt) can eliminate the need for negative igbt gate drive in many applications as shown in figure 19. care should be taken with such a pc board design to avoid routing the igbt collector or emitter traces close to the HCPL-J314 input as this can result in unwanted coupling of transient signals into the input of HCPL-J314 and degrade performance. (if the igbt drain must be routed near the HCPL-J314 input, then the led should be reverse biased when in the off state, to prevent the transient signals coupled from the igbt drain from turning on the HCPL-J314.) an external clamp diode may be connected between pins 5 and 6/7 for the protection of HCPL-J314, in the case of igbts switching inductive load. figure 19. recommended led drive and application circuit for hcpl-314j. + hvdc 3-phase ac - hvdc 0.1 ? v cc = 15 v 1 3 + 2 4 8 6 7 5 HCPL-J314 rg q1 q2 270 w +5 v control input 74xxx open collector
12 selecting the gate resistor (rg) step 1: calculate r g minimum from the i ol peak specification. the igbt and rg in figure 19 can be analyzed as a simple rc circuit with a voltage supplied by the HCPL-J314. the v ol value of 5 v in the previous equation is the v ol at the peak current of 0.6a. (see figure 6). step 2: check the HCPL-J314 power dissipation and increase rg if necessary. the HCPL-J314 total power dissipation (p t ) is equal to the sum of the emitter power (p e ) and the output power (p o ). p t = p e + p o p e = i f v f duty cycle p o = p o(bias) + p o ( switching ) = i cc v cc + e sw ( r g ,q g) f = ( i ccbias + k icc q g f ) v cc + e sw ( r g ,q g) f where k icc q g f is the increase in i cc due to switching and k icc is a constant of 0.001 ma/(nc*khz). for the circuit in figure 19 with i f (worst case) = 10 ma, rg = 32 w , max duty cycle = 80%, qg = 100 nc, f = 20 khz and t amax = 85 c: p e = 10 ma 1.8 v 0.8 = 14 mw p o = (3 ma + (0.001 ma /( nc khz )) 20 khz 100 nc ) 24 v + 0.4 m j 20 khz = 128 mw < 260 mw ( p o ( max ) @ 85 c ) the value of 3 ma for i cc in the previous equation is the max. i cc over entire operating temperature range. since p o for this case is less than p o(max) , rg = 32 w is alright for the power dissipation. = 24 v C 5 v 0.6 a = 32 w figure 20. energy dissipated in the HCPL-J314 and for each igbt switching cycle. led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector ic as shown in figure 21. the HCPL-J314 improves cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and opto- coupler pins 5-8 as shown in figure 22. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded optocoupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off ) during common mode transients. for example, the recommended application circuit (figure 19), can achieve 10 kv/ m s cmr while minimizing component complexity. techniques to keep the led in the proper state are discussed in the next two sections. rg 3 v cc C v ol i olpeak esw ?energy per switching cycle ?? 0 0 rg ?gate resistance ? w 100 1.5 20 4.0 40 1.0 60 80 3.5 qg = 50 nc qg = 100 nc qg = 200 nc qg = 400 nc 3.0 2.0 0.5 2.5
13 figure 21. optocoupler input to output capacitance model for unshielded optocouplers. figure 22. optocoupler input to output capacitance model for shielded optocouplers. figure 23. equivalent circuit for figure 17 during common mode transient. figure 24. not recommended open collector drive circuit. figure 25. recommended led drive circuit for ultra-high cmr ipm dead time and propagation delay specifications. 1 3 2 4 8 6 7 5 c ledp c ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield c ledo1 c ledo2 rg 1 3 v sat 2 4 8 6 7 5 + v cm i ledp c ledp c ledn shield * the arrows indicate the direction of current flow during ?v cm /dt. +5 v + v cc = 18 v ?? ?? 0.1 ? + 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v q1 i ledn 1 3 2 4 8 6 7 5 c ledp c ledn shield +5 v
14 cmr with the led on (cmr h ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. a minimum led current of 8 ma provides adequate margin over the maximum i flh of 5 ma to achieve 10 kv/ m s cmr. cmr with the led off (cmr l ) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a -dv cm /dt transient in figure 23, the current flowing through c ledp also flows through the r sat and v sat of the logic gate. as long as the low state voltage developed across the logic gate is less than v f(off) the led will remain off and no common mode failure will occur. the open collector drive circuit, shown in figure 24, can not keep the led off during a +dv cm /dt transient, since all the current flowing through c ledn must be supplied by the led, and it is not recommended for applications requiring ultra high cmr 1 performance. the alternative drive circuit which like the recommended application circuit (figure 19), does achieve ultra high cmr performance by shunting the led in the off state. ipm dead time and propagation delay specifications the HCPL-J314 includes a propagation delay difference (pdd) specification intended to help designers minimize dead time in their power inverter designs. dead time is the time high and low side power transistors are off. any overlap in ql and q2 conduction will result in large currents flowing through the power devices from the high-voltage to the low- voltage motor rails. to minimize dead time in a given design, the turn on of led2 should be delayed (relative to the turn off of led1) so that under worst- case conditions, transistor q1 has just turned off when transistor q2 turns on, as shown in figure 26. the amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, pdd max, which is specified to be 500 ns over the operating temperature range of -40 to 100 c. delaying the led signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in figure 27. the maximum dead time for the HCPL-J314 is 1 m s (= 0.5 m s - (-0.5 m s)) over the operating temperature range of -40 c to 100 c. note that the propagation delays used to calculate pdd and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical igbts.
15 figure 26. minimum led skew for zero dead time. figure 27. waveforms for dead time. t plh min maximum dead time (due to optocoupler) = (t phl max - t phl min ) + (t plh max - t plh min ) = (t phl max - t plh min ) ?(t phl min - t plh max ) = pdd* max ?pdd* min *pdd = propagation delay difference note: for dead time and pdd calculations all propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on t phl min t phl max t plh max pdd* max (t phl- t plh ) max t phl max t plh min pdd* max = (t phl - t plh ) max = t phl max - t plh min *pdd = propagation delay difference note: for pdd calculations the propagation delays are taken at the same temperature and test conditions. v out1 i led2 v out2 i led1 q1 on q2 off q1 off q2 on
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies 5968-7901e (11/99)

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